The present invention relates to a semiconductor design technology, and more particularly, to a semiconductor memory device for generating a column selection signal that is activated in response to a read operation and a write operation.
In general, a semiconductor memory device such as a Double Data Rate Synchronous DRAM (DDR SDRAM) includes more than several million memory cells for storing data and stores or outputs data according to a command from a central processing unit (CPU). That is, when the CPU requests a write operation, data is stored in a memory cell corresponding to an address inputted from the CPU. When the CPU requests a read operation, data stored in a memory cell corresponding to the input address is outputted. In other words, data received through an input/output pad from the outside is inputted to a memory cell through a data input path in case of a write operation. In case of a read operation, data stored in a memory cell passes through a data output path and is outputted to the outside through the input/output pad.
FIG. 1 is a diagram for describing a read operation and a write operation of a conventional semiconductor memory device. Although a semiconductor memory device is generally designed to include several million memory cells, one memory cell is shown for illustration. Here, a reference numeral 110 is assigned to the memory cell.
As shown, a read operation of the semiconductor memory device will be described.
At first, when a word line WL is selected by decoding a row address inputted according to a row command signal and the selected word line WL is activated, a cell transistor T1 of a memory cell 110 is turned on. Then, data stored in a cell capacitor C1 is charge-shared to a pre-charged bit line pair BL and /BL. The bit line BL and the complementary bit line /BL have a very small electric potential difference through a charge sharing operation. Here, a pre-charged voltage level has a ½ voltage level of a core voltage which is an internal voltage.
A bit line sense amplifier 120 senses very small electric potential of the bit line BL and the complementary bit line /BL and amplifies the sensed electric potential. In other words, if the electric potential of the bit line BL is higher than the electric potential of the complementary bit line /BL, the bit line BL is amplified to a full-up supply voltage RTO, and the complementary bit line BL is amplified to a full-down supply voltage SB. On the contrary, if the electric potential of the bit line BL is lower than the electric potential of the complementary bit line /BL, the bit line BL is amplified into a full down supply voltage SB, and the complementary bit line /BL is amplified to a full up supply voltage RTO.
Meanwhile, if a column selection signal YI is selected by decoding a column address inputted according to a column command signal, a column selector 130 is activated. Then, the bit line pair BL and /BL is connected to a segment input/output line pair SIO and /SIO. That is, amplified data from the bit line BL is transferred to a segment input/output line SIO, and amplified data from the complementary bit line /BL is transferred to a complementary segment input/output line /SIO.
Then, if an input/output switching unit 140 is activated in response to an input/output control signal CTR_IO corresponding to a column address, the segment input/output line pair SIO and /SIO is connected to the local input/output line pair LIO and /LIO. That is, data transferred to the segment input/output line SIO is transferred to the local input/output line LIO, and data transferred to the complementary segment input/output line /SIO is transferred to the complementary local input/output line /LIO. The read driver 150 drives a global input/output line GIO according to data transferred through the local input/output line pair LIO and /LIO.
Finally, data stored in the memory cell 110 is transferred from the bit line pair BL and /BL to a segment input/output line pair SIO and /SIO in response to a column selection signal YI, data transferred to the segment input/output line pair SIO and /SIO is transferred to the local input/output line pair LIO and /LIO in response to an input/output control signal CTR_IO, and data transferred to the local input/output line pair LIO and /LIO is transferred to a global input/output line GIO by the read driver 150. The transferred data is finally outputted to the outside through a corresponding input/output pad (not shown).
Meanwhile, in a write operation, data applied to the outside is transferred to an opposite direction of a read operation. That is, data applied through the input/output pad is transferred from the global input/output line GIO to the local input/output line pair LIO and /LIO by a write driver 160. The data is also transferred from the local input/output line pair LIO and /LIO to the segment input/output line pair SIO and /SIO, and from the segment input/output line pair SIO and /SIO to the bit line pair BL and /BL. Finally, the data is stored in the memory cell 110.
FIG. 2 is a block diagram illustrating configuration for generating a column selection signal YI of FIG. 1. That is, FIG. 2 illustrates an internal command signal generator 210, a pulse signal generator 230 and an address decoder 250.
The internal command signal generator 210 generates a read internal command signal CASPB_RD and a write internal command signal CASPB_WT in response to a column command signal CMD that is activated according to an external command signal from the outside. Here, the column command signal CMD is a signal activated for a read operation and a write operation of a semiconductor memory device. The read internal command signal CASPB_RD is a pulse signal activated in a read operation of a semiconductor memory device, and the write internal command signal CASPB_WT is a pulse signal activated in a write operation of a semiconductor memory device.
The pulse signal generator 230 generates a pulse signal AYP in response to the read internal command signal CASPB_RD and the write internal command signal CASPB_WT. Although it will be described again, the pulse signal AYP has a predetermined pulse width, and this pulse width is used as a reference that defines an active region of the column selection signal YI.
The address decoder 250 decodes address information ADD<0:N> where N is a natural number, and generates a column selection signal YI by reflecting the decoded address information to the pulse signal AYP. The column selection signal YI also has a pulse form, and a pulse width thereof corresponds to the pulse width of the pulse signal AYP. For better comprehension and easy description, one column selection signal YI is shown, and the column selection signal YI is one of a plurality of signals generated by decoding the column address signal ADD<0:N>.
FIG. 3 is a waveform for describing an operation waveform of each signal in FIG. 2 in a write operation. The waveform illustrates an external clock signal CLK, a write internal command signal CASPB_WT, a pulse signal AYP, and a column selection signal YI. And data applied to the bit line pair BL and /BL of FIG. 1 is shown. Hereinafter, the waveform will be described with reference to FIGS. 1 to 3. For better comprehension and easy description, it is assumed that data corresponding to a logic ‘high’ level is applied to the bit line BL before a write operation of data corresponding to a logic ‘low’ level.
At first, if an active command ACT is applied, a word line WL is activated, and the bit line and the complementary bit line BL and /BL have a very small potential difference through a charge sharing operation. Then, data applied to the bit line pair BL and /BL is amplified by the bit line sensing amplifier 120.
If a write command WT is applied, the write internal command signal CASPB_WT is activated. Accordingly, a pulse signal AYP having a predetermined pulse width is activated. The generated pulse signal AYP is referred to decide a pulse width of a column selection signal YI. Although it is not shown in FIG. 3, data of a logic ‘low’ level inputted from the outside with a write command WT is transferred to the segment input/output line pair SIO and /SIO through the global input/output line GIO and the local input/output line pair LIO and /LIO. Therefore, if the bit line pair BL and /BL is connected to the segment input/output line pair SIO and /SIO in an active region where the column selection signal YI is activated to the logic ‘high’ level, data applied to the segment input/output line pair SIO and /SIO is transferred to the bit line pair BL and /BL. As shown, the bit line BL is changed from data corresponding to logic ‘high’ level to data corresponding to logic ‘low’ level in a region where a column selection signal YI is activated to logic ‘high’ level, and a complementary bit line /BL is changed from data corresponding to logic ‘low’ level to data corresponding to logic ‘high’ level.
Here, a time taken for changing data applied to the bit line pair BL and /BL in a write operation may be changed according to an external supply voltage applied to a semiconductor memory device. That is, a time taken for raising a voltage level of the complementary bit line /BL from a voltage level corresponding to logic ‘low’ level to a voltage level corresponding to logic ‘high’ level is changed according to the external supply voltage. In case of a high voltage level of an external supply voltage, the time taken for raising the voltage level becomes shortened in proportion to the high voltage level of the external supply voltage. In case of a low voltage level of an external supply voltage, the time taken for raising the voltage level becomes extended in proportion to the low voltage level.
In case of a conventional semiconductor memory device, a pulse width of a column selection signal YI is fixed. Therefore, the bit line pair BL and /BL is connected to the segment input/output line pair SIO and /SIO only for a predetermined time although a voltage level of an external supply voltage is changed. It may cause following two problems.
At first, if a voltage level of an external supply voltage is low, a time taken for changing data of the bit line pair BL and /BL becomes extended in proportion to a low voltage level of the external supply voltage. Since the bit line pair BL and /BL is connected to the segment input/output line pair SIO and /SIO only for a scheduled time, data of the bit line pair BL and /BL may not be completely changed. It means that data is not accurately transferred to the bit line pair BL and /BL. Finally, desired data cannot be stored in the memory cell 110 (See FIG. 1).
Secondly, if a voltage level of an external supply voltage is high, a time taken for changing data of the bit line pair BL and /BL is shortened in proportion to a high voltage level of the external supply voltage. However, a semiconductor memory device may consume electric power unnecessarily because the time of connecting the bit line pair BL and /BL with the segment input/output line pair SIO and /SIO is unnecessary long. Furthermore, circuit operation efficiency may be deteriorated because the column selection signal YI is activated for unnecessarily long time.